The present invention relates to generally a digital code transmission system and more particularly to a digital code monitor system wherein check codes are inserted into the time slots formed by the bit rate conversion of the information pulse train.
The conventional digital code monitor systems of the type described above may be divided into the following three systems;
1. THE FIRST SYSTEM IN WHICH A SPECIFIC PATTERN SUCH AS A PSEUDO RANDOM PATTERN CONSISTING OF MORE THAN ONE DIGIT SIGNAL IS TRANSMITTED FOR EACH FRAME WHICH EQUALS THE REPETITIVE INTERVAL OF TIME SLOTS NEWLY FORMED BY THE BIT RATE CONVERSION, AND IS DETECTED FOR MONITORING OF ITS ERROR ON A RECEIVING SIDE;
2. IN THE SECOND SYSTEM IN WHICH THE COMBINATION OF AN INFORMATION PULSE TRAIN AND A CHECK CODE IN EACH FRAME HAS SPECIFIC ADD OR EVEN CHARACTERISTICS ODD OR EVEN IN THE SPECIFIC STATE OF THE Q-ary and R-level code, for instance, the state of "1" or "0" in the binary code, is transmitted, and said specific characteristic is checked.
3. IN THE THIRD SYSTEM THE NUMBER OF DIGITS IN THE SPECIFIC STATE OF THE Q-ary and R-level code, for instance, the number of "1" or "0" in the binary code, in each frame are summed, and a check code is formed based upon the sum is inserted into the time slots formed by the bit rate conversion. The resulting signal is transmitted, and compared with a check code formed in a manner substantially similar to that used in the transmitting equipment.
In the monitor systems of the types described, the check codes or monitor signals are formed based upon the information pulse train whose bit rate is converted in the transmitting equipment so that the section in a transmission system which can be monitored by any of the above three monitor systems is limited from the point immediately after the information pulse trains are subjected to the bit rate conversion in the transmitting equipment to the point immediately before the bit rate converted pulse train are restored to their normal bit rate in the receiving equipment. Therefore, a malfunction in the transmission systems before and after the bit rate converters cannot be detected so that the automatic switching to an auxiliary circuit or circuits cannot be made. Furthermore, it takes a long time before the malfunction can be detected.